Deep implanted region for a cmos imager

ABSTRACT

A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of semiconductordevices and, in particular, to high quantum efficiency CMOS imagesensors.

BACKGROUND OF THE INVENTION

[0002] CMOS imagers have been increasingly used as low cost imagingdevices. A CMOS imager circuit includes a focal plane array of pixelcells, each one of the cells including either a photodiode, a photogateor a photoconductor overlying a doped region of a substrate foraccumulating photo-generated charge in the underlying portion of thesubstrate. A readout circuit is connected to each pixel cell andincludes a charge transfer section formed on the substrate adjacent thephotodiode for transferring electrons to a sensing node, typically afloating diffusion node, connected to the gate of a source followeroutput transistor. The imager may include at least one transistor fortransferring charge from the charge accumulation region of the substrateto the floating diffusion node and also has a transistor for resettingthe diffusion node to a predetermined charge level prior to chargetransfer.

[0003] In a conventional CMOS imager, the active elements of a pixelcell perform the necessary functions of: (1) photon to chargeconversion; (2) accumulation of image charge; (3) transfer of charge tothe floating diffusion node accompanied by charge amplification; (4)resetting the floating diffusion node to a known state before thetransfer of charge to it; (5) selection of a pixel for readout; and (6)output and amplification of a signal representing pixel charge. Thecharge at the floating diffusion node is converted to a pixel outputvoltage by the source follower output transistor. The photosensitiveelement of a CMOS imager pixel is typically either a depleted p-njunction photodiode or a field induced depletion region beneath aphotogate.

[0004] CMOS imaging devices of the type discussed above are generallyknown and discussed in, for example, Nixon et al., “256.times.256 CMOSActive Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-StateCircuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOSActive Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol.41(3), pp. 452-453 (1994), the disclosures of which are incorporated byreference herein.

[0005] A schematic top view of a semiconductor wafer fragment of anexemplary CMOS sensor pixel four-transistor (4T) cell 10 is illustratedin FIG. 1. As it will be described below, the CMOS sensor pixel cell 10includes a photo-generated charge accumulating area 21 in an underlyingportion of the substrate. This area 21 is formed as a pinned diode 11(FIG. 2). The pinned photodiode is termed “pinned” because the potentialin the photodiode is pinned to a constant value when the photodiode isfully depleted. It should be understood, however, that the CMOS sensorpixel cell 10 may include a photogate, a photoconductor or other imageto charge converting device, in lieu of a pinned photodiode, as theinitial accumulating area 21 for photo-generated charge.

[0006] The CMOS image sensor 10 of FIG. 1 has a transfer gate 30 fortransferring photoelectric charges generated in the charge accumulatingregion 21 to a floating diffusion region (sensing node) 25. The floatingdiffusion region 25 is further connected to a gate 50 of a sourcefollower transistor. The source follower transistor provides an outputsignal to a row select access transistor having gate 60 for selectivelygating the output signal to terminal 32. A reset transistor having gate40 resets the floating diffusion region 25 to a specified charge levelbefore each charge transfer from the charge accumulating region 21.

[0007] A cross-sectional view of the exemplary CMOS image sensor 10 ofFIG. 1 taken along line 2-2′ is illustrated in FIG. 2. The chargeaccumulating region 21 is formed as a pinned photodiode 11 which has aphotosensitive or p-n-p junction region formed by a p-type layer 24, ann-type region 26 and the p-type substrate 20. The pinned photodiode 11includes two p-type regions 20, 24 so that the n-type photodiode region26 is fully depleted at a pinning voltage. Impurity doped source/drainregions 22 (FIG. 1), preferably having n-type conductivity, are providedon either side of the transistor gates 40, 50, 60. The floatingdiffusion region 25 adjacent the transfer gate 30 is also preferablen-type.

[0008]FIG. 2 also illustrates trench isolation regions 15 formed in theactive layer 20 adjacent the charge accumulating region 21. The trenchisolation regions 15 are typically formed using a conventional STIprocess or by using a Local Oxidation of Silicon (LOCOS) process. Atranslucent or transparent insulating layer 55 formed over the CMOSimage sensor 10 is also illustrated in FIG. 2. Conventional processingmethods are used to form, for example, contacts 32 (FIG. 1) in theinsulating layer 55 to provide an electrical connection to thesource/drain regions 22, the floating diffusion region 25, and otherwiring to connect to gates and other connections in the CMOS imagesensor 10.

[0009] Generally, in CMOS image sensors such as the CMOS image sensorcell 10 of FIGS. 1-2, incident light causes electrons to collect inregion 26. A maximum output signal, which is produced by the sourcefollower transistor having gate 50, is proportional to the number ofelectrons to be extracted from the region 26. The maximum output signalincreases with increased electron capacitance or acceptability of theregion 26 to acquire electrons. The electron capacity of pinnedphotodiodes typically depends on the doping level of the image sensorand the dopants implanted into the active layer.

[0010] Minimizing dark current in the photodiode is important in CMOSimage sensor fabrication. Dark current is generally attributed toleakage in the charge collection region 21 of the pinned photodiode 11,which is strongly dependent on the doping implantation conditions of theCMOS image sensor. In addition, defects and trap sites inside or nearthe photodiode depletion region strongly influence the magnitude of darkcurrent generated. In sum, dark current is a result of current generatedfrom trap sites inside or near the photodiode depletion region;band-to-band tunneling induced carrier generation as a result of highfields in the depletion region; junction leakage coming from the lateralsidewall of the photodiode; and leakage from isolation corners, forexample, stress induced and trap assisted tunneling.

[0011] CMOS imagers also typically suffer from poor signal to noiseratios and poor dynamic range as a result of the inability to fullycollect and store the electric charge collected in the region 26. Sincethe size of the pixel electrical signal is very small due to thecollection of photons in the photo array, the signal to noise ratio anddynamic range of the pixel should be as high as possible.

[0012] There is needed, therefore, an improved active pixel photosensorfor use in a CMOS imager that exhibits reduced dark current andincreased photodiode capacitance, while also having low pixel-to-pixelcross-talk. A method of fabricating an active pixel photosensorexhibiting these improvements is also needed.

BRIEF SUMMARY OF THE INVENTION

[0013] In one aspect, the invention provides a deep implanted region ofa first conductivity type located below a transistor array of a pixelsensor cell and laterally adjacent a doped region of a secondconductivity type of a photodiode of the pixel sensor cell. The deepimplanted region reduces surface leakage and dark current and increasesthe capacitance of the photodiode by acting as a reflective barrier toelectrons generated by light in the doped region of the secondconductivity type of the photodiode. The deep implanted region alsoprovides optimal transfer of charges from the charge collection regionto a floating diffusion region adjacent the gate of the transfertransistor.

[0014] In another aspect, the invention provides a method of forming adeep implanted region below a transistor array of a pixel sensor celland laterally adjacent a charge collection region of a photodiode of thepixel sensor cell. The deep implanted region is formed by conducting atleast one deep implant for implanting desired dopants below thetransistor array and subsequent to the patterning of the transistor gatestructures of the pixel sensor cell.

[0015] These and other features and advantages of the invention will bemore apparent from the following detailed description that is providedin connection with the accompanying drawings and illustrated exemplaryembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a top plan view of an exemplary CMOS image sensor pixel.

[0017]FIG. 2 is a schematic cross-sectional view of the CMOS imagesensor of FIG. 1 taken along line 2-2′.

[0018]FIG. 3 is a schematic cross-sectional view of a CMOS image sensorpixel fabricated in accordance with the present invention and at aninitial stage of processing.

[0019]FIG. 4 is a schematic cross-sectional view of a CMOS image sensorfragment of FIG. 3 at a stage of processing subsequent to that shown inFIG. 3.

[0020]FIG. 5 is a schematic cross-sectional view of a CMOS image sensorpixel of FIG. 3 at a stage of processing subsequent to that shown inFIG. 4.

[0021]FIG. 6 is a schematic cross-sectional view of a CMOS image sensorpixel of FIG. 3 at a stage of processing subsequent to that shown inFIG. 5.

[0022]FIG. 7 illustrates a schematic diagram of a computer processorsystem incorporating a CMOS image sensor fabricated according to thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0024] The terms “wafer” and “substrate” are to be understood as asemiconductor-based material including silicon, silicon-on-insulator(SOI) or silicon-on-sapphire (SOS) technology, doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures.Furthermore, when reference is made to a “wafer” or “substrate” in thefollowing description, previous process steps may have been utilized toform regions or junctions in or over the base semiconductor structure orfoundation. In addition, the semiconductor need not be silicon-based,but could be based on silicon-germanium, silicon-on-insulator,silicon-on-saphire, germanium, or gallium arsenide, among others.

[0025] The term “pixel” refers to a picture element unit cell containinga photosensor and transistors for converting electromagnetic radiationto an electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein and,typically, fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion.

[0026] Referring now to the drawings, where like elements are designatedby like reference numerals, FIGS. 3-6 illustrate exemplary embodimentsof methods of forming a four-transistor (4T) pixel sensor cell 100 (FIG.6) having a deep implanted region or well 199 formed below a transistorarray 101 and adjacent a charge collection region 126 of photodiode 188.As explained in detail below, the deep implanted region 199 is formed byimplanting dopants of a first conductivity type below the transistorarray 101 and in the bulk substrate 110. The deep implanted region 199is adjacent a doped region 126 of a second conductivity type forming thecharge collection region of the photodiode 188 and acts as a reflectivebarrier to electrons generated by light in the doped region 126 of thesecond conductivity type.

[0027] It should be noted that, although the invention will be describedbelow in connection with use in a four-transistor (4T) pixel cell, theinvention also has applicability to a three-transistor (3T) cell whichdiffers from the 4T cell in the omission of a charge transfer transistordescribed below, as known in the art. In this case, the deep implant isstill located adjacent the charge collection region of a photodiode.

[0028]FIG. 3 illustrates a substrate 110 along a cross-sectional view ofthe structure of FIG. 1 taken along line 3-3′. For exemplary purposes,the substrate 110 is a silicon substrate. However, as noted above, theinvention has equal application to other semiconductor substrates. FIG.3 also illustrates a multi-layered transfer and reset gate stacks 130and 140, respectively, formed over the silicon substrate 110 and as partof transistor array 101. The transfer and reset gate stacks 130 comprisea first gate oxide layer 131 of grown or deposited silicon oxide on thesilicon substrate 110, a conductive layer 132 of doped polysilicon orother suitable conductor material, and a second insulating layer 133,which may be formed of, for example, silicon oxide (silicon dioxide),nitride (silicon nitride), oxynitride (silicon oxynitride), ON(oxide-nitride), NO (nitride-oxide), or ONO (oxide-nitride-oxide). Thefirst and second insulating layers 131, 133 and the conductive layer 132may be formed by conventional deposition methods, for example, chemicalvapor deposition (CVD) or plasma enhanced chemical vapor deposition(PECVD), among many others.

[0029] If desired, a silicide layer (not shown) may be also formed inthe multi-layered gate stacks 130, 140 between the conductive layer 132and the second insulating layer 133. Advantageously, the gate structuresof all other transistors in the imager circuit design may have thisadditionally formed silicide layer. This silicide layer may be titaniumsilicide, tungsten silicide, cobalt suicide, molybdenum silicide, ortantalum silicide. The silicide layer could also be a barrierlayer/refractory metal such as TiN/W or WN_(x)/W or it could be entirelyformed of WN_(x). FIG. 3 also illustrates insulating sidewall spacers134 formed on the sides of the transfer gate 130 and of the reset gate140. The sidewall spacers 134 may be formed, for example, of silicondioxide, silicon nitride, silicon oxynitride, ON, NO, ONO or TEOS, amongothers.

[0030]FIG. 3 also illustrates isolation regions 150 which are formedwithin the substrate 110 and are filled with a dielectric material,which may be an oxide material, for example a silicon oxide such as SiOor SiO₂, oxynitride, a nitride material such as silicon nitride, siliconcarbide, or other suitable dielectric materials. In a preferredembodiment, however, the isolation regions 150 are shallow trenchisolation regions and the dielectric material is a high density plasma(HDP) oxide, a material which has a high ability to effectively fillnarrow trenches. Thus, for simplicity, reference to the isolationregions 150 will be made in this application as to the shallow trenchisolation regions 150. The shallow trench isolation regions 150 have adepth of about 1,000 to about 4,000 Angstroms, more preferably of about2,000 Angstroms.

[0031] Although FIGS. 3-6 illustrate only a portion of the substrate 110with only two shallow trench isolation regions 150, it must beunderstood that the present invention contemplates the simultaneousformation of more than two shallow trench isolation structures atvarious locations on the substrate 110 to isolate the pixels one fromanother and to isolate other structures as well.

[0032] In addition, if desired, a thin insulating layer (not shown) maybe formed on the sidewalls and bottom of the shallow trench before thefilling of the trench with the dielectric material which, as notedabove, is preferably a high density plasma (HDP) oxide. The thininsulating layer may be formed of an oxide or of silicon nitride, forexample, to aid in smoothing out the corners in the bottom of the trenchand to reduce the amount of stress in the dielectric material used tolater fill in the trenches.

[0033] Referring now to FIG. 4, a p-n-p photodiode 188 is formed byregions 124, 126 and 120 within the substrate 110. The p-type dopedlayer 120 is formed in the areas of the substrate 110 directly beneaththe active area of the pixel cell by conducting a dopant implantationwith a dopant of a first conductivity type, which for exemplary purposesis p-type. The p-type doped layer 120 may be formed subsequent to theformation of the shallow trench isolation (STI) 150 and of the gatestacks 130, 140. However, it must be understood that the p-type dopedlayer 120 may be also formed prior to the formation of the shallowtrench isolation (STI) 150 and/or gate stacks 130, 140. The dopantconcentration in the p-type doped layer 120 is within the range of about1×10¹⁵ to about 5×10¹⁸ atoms per cm³, and is preferably within the rangeof about 1×10¹⁶ to about 5×10¹⁷ atoms per cm³.

[0034] The n-type region 126 (FIG. 4) is formed by implanting dopants ofa second conductivity type, which for exemplary purposes is n-type, inthe area of the substrate directly beneath the active area of the pixelcell. The implanted n-doped region 126 forms a photosensitive chargestorage region for collecting photogenerated electrons. Ion implantationmay be conducted by placing the substrate 110 in an ion implanter, andimplanting appropriate n-type dopant ions into the substrate 110 at anenergy of 20 keV to 300 keV to form n-doped region 126. N-type dopantssuch as arsenic, antimony, or phosphorous may be employed. The dopantconcentration in the n-doped region 126 (FIG. 4) is within the range ofabout 5×10¹⁵ to about 5×10¹⁶ atoms per cm³, and is preferably within therange of about 1×10¹⁶ to about 5×10¹⁶ atoms per cm³.

[0035] The p-type pinned surface layer 124 is also formed by conductinga dopant implantation with a dopant of the first conductivity type,which for exemplary purposes is p-type, so that p-type ions areimplanted into the area of the substrate over the implanted n-typeregion 126 and between the transfer gate 130 and shallow trenchisolation region 150. The dopant concentration in the p-type pinnedsurface layer 124 is within the range of about 1×10¹⁷ to about 5×10¹⁸atoms per cm³, and is preferably within the range of about 1×10¹⁸ atomsper cm³.

[0036] Subsequent to the formation of the p-n-p photodiode 188 and ofthe transfer and reset gates 130, 140, a photoresist layer 167 (FIG. 5)is formed over the p-n-p photodiode 188 and the transfer and reset gates130, 140, to a thickness of about 1,000 Angstroms to about 10,000Angstroms. The photoresist layer 167 (FIG. 5) is patterned with a mask(not shown) to obtain an opening 168 (FIG. 5) which, on one side,partially extends over transfer gate 130 by an offset distance W, asillustrated in FIG. 5 and, on the other side, is approximatelycoincident with the edge of the STI region 150 (the left most STI regionin FIG. 5).

[0037] The offset distance W (FIG. 5) may be tailored according to thephotodiode and transfer gate characteristics to achieve an optimaldopant gradient from the n-type charge collection region 126 of thephotodiode 188 to n-type floating diffusion region 129. The offsetdistance W may be about 10% to about 90% the length L (FIG. 5) of thetransfer gate 130, more preferably of about 25% to about 75% the lengthL of the transfer gate 130. For example, a transfer gate having a lengthL of about 0.5 microns may require an offset distance W of about 50% thelength of the transfer gate, that is, of about 0.25 microns. Similarly,a transfer gate having a length L of about 0.3 microns may require anoffset distance W of about 25% the length of the transfer gate, that is,of about 0.13 microns.

[0038] Next, the structure of FIG. 5 is subjected to a deep maskeddopant implantation 169 (FIG. 5) with a dopant of the first conductivitytype, which for exemplary purposes is p-type. This way, p-type ions areimplanted through the opening 168 (FIG. 5) to form a p-type deepimplanted region 199 located below the transistor array 101 and incontact with the n-type doped region 126, as illustrated in FIG. 6.Although, the p-type deep implanted region 199 may be formed in contactwith the n-type doped region 126, as shown in FIG. 6, the invention isnot limited to this embodiment. Accordingly, the present invention alsocontemplates the formation of a p-type deep implanted region adjacentand spaced from the n-type doped region 126, in accordance with thephotodiode and transfer gate characteristics.

[0039] The deep dopant implantation 169 is conducted to implant p-typeions, such as boron, beryllium, indium or magnesium, into an area of thesubstrate 110 located right below the transistor array 101. The dopantimplantation 169 may be conducted by placing the substrate 110 in an ionimplanter and implanting appropriate p-type dopant ions through theopening 168 (FIG. 5) into the substrate 110 at an energy of 50 keV toabout 150 keV, more preferably of about 90 keV, to form the deep p-typeimplanted region or well 199. P-type dopants, such as boron, beryllium,indium or magnesium, may be employed for the first implant. The dopantconcentration in the deep p type implanted region 199 (FIG. 6) is withinthe range of about 1×10¹⁶ to about 1×10¹⁷ atoms per cm³, more preferablyof about 5×10¹⁵ to about 5×10¹⁶ atoms per cm³.

[0040] The photoresist layer 167 is then removed by conventionaltechniques, such as oxygen plasma for example, or by flooding thesubstrate 110 with UV radiation, to complete the formation of deepimplanted region 199 (FIG. 6) and the formation of the pixel sensor cell100 (FIG. 6).

[0041] The deep implanted region 199 of FIG. 6 acts as a reflectivebarrier to electrons generated by light in the n-doped region 126 of thep-n-p photodiode 188. When light radiation in the form of photonsstrikes the n-doped photosite region 126, photo-energy is converted toelectron-hole pairs. For the case of an n-doped photosite in a p-n-pphotodiode, it is the electrons that are accumulated in the n-dopedregion 126. For the case of a p-doped photosite in an n-p-n photodiode,it is the holes that are accumulated in the n-doped region 126. Thus, inthe exemplary embodiment described above having n-channel devices formedin the p-type well 120, electrons are accumulated in the n-doped region126. The deep implanted region 199 located below the transistor array101 acts to reduce carrier loss to the substrate 110 by forming aconcentration gradient that modifies the band diagram and serves toreflect electrons back towards the n-doped photosite region 126, therebyreducing cross-talk between adjacent pixel sensor cells.

[0042] In addition to providing a reflective barrier to electronsgenerated by light in the charge collection region 126, the deepimplanted region 199 creates a dopant gradient from the photodiode 188to the floating diffusion region 129 (FIG. 6). As known in the art, onefigure of merit (FoM) of the transfer gate 130 is the efficiency of thegate 130 to transfer accumulated charge from the photodiode region 126to the floating diffusion region 129. One way of increasing the transferefficiency of the gate 130 is to physically apply a potential gradientVt from the photodiode region 126 to the floating diffusion region 129.The present invention provides another way of increasing the transferefficiency of the gate 130, that is, by creating a dopant gradientconferred by the deep implanted region 199 (FIG. 6) that optimizes thetransfer of charge from the photodiode region 126 to the floatingdiffusion region 129.

[0043] The deep implanted region 199 also providesphotodiode-to-photodiode isolation, for example, isolation of thephotodiode 188 from an adjacent photodiode (not shown) located on theother side of the shallow trench isolation region 150.

[0044] Although FIGS. 3-6 illustrate deep implanted region 199 formed byconducting only one implant, the invention is not limited to thisembodiment and contemplates the formation of a deep implanted regionformed by conducting a plurality “i” of such deep implants. Preferably,the number “i” of implants and the dopant concentration of each implantmay be tailored so that depth D (FIG. 6) of the deep implanted region199 is equal to or greater than the depth of the n-type doped region 126of the photodiode 188. This way, one skilled in the art may tailor thedosage and implant energy of each of the “i” implants to form the deepimplanted region 199 which acts as a barrier to fully reflect electronsback toward the n-doped photosite region 126 and provide completeisolation of the photodiode 188 from adjacent photodiodes. Preferably,the depth D of the p-type implanted region 199 of the substrate 110 maybe of about 0.5 microns to about 7.0 microns, more preferably of about1.0 microns to about 5.0 microns.

[0045] The remaining devices of the pixel sensor cell 100, including thesource follower transistor and row select transistor shown in FIG. 1 asassociated with respective gates 50 and 60 and source/drain regions oneither sides of the gates 40, 50, 60, are also formed by well-knownmethods. Conventional processing steps may be also employed to formcontacts and wiring to connect transistor gate and source and drainregions of pixel cell 100. For example, the entire surface may becovered with a passivation layer 155 (FIG. 6) of, e.g., silicon dioxide,BSG, PSG, or BPSG, which is CMP planarized and etched to provide contactholes, which are then metallized to provide contacts to the reset gate,transfer gate and other pixel structures, as needed. Conventionalmultiple layers of conductors and insulators to other circuit structuresmay also be used to interconnect the internal structures of the pixelsensor cell and to connect the pixel cell structures to other circuitryassociated with the pixel array.

[0046] A typical processor based system 600, which has a connected CMOSimager having pixels constructed according to the invention isillustrated in FIG. 7. A processor based system is exemplary of a systemhaving digital circuits which could include CMOS imagers. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision, vehicle navigation, video phone, surveillancesystem, auto focus system, star tracker system, motion detection system,image stabilization system and data compression system forhigh-definition television, all of which can utilize the presentinvention.

[0047] A processor based system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 644, for example, amicroprocessor, that communicates with an input/output (I/O) device 646over a bus 652. The CMOS imager 642 communicates with the system overbus 652. The computer system 600 also includes random access memory(RAM) 648, and may include peripheral devices such as a floppy diskdrive 654, and a compact disk (CD) ROM drive 656 or a flash memory card657 which also communicate with CPU 644 over the bus 652. It may also bedesirable to integrate the processor 654, CMOS image sensor 642 andmemory 648 on a single IC chip.

[0048] Although the above embodiments have been described with referenceto the formation of a p-n-p photodiode, such as the p-n-p photodiode 188(FIGS. 3-6) having an n-type charge collection region formed adjacent adeep implanted region 199 formed by implantation below a transistorarray, it must be understood that the invention is not limited to thisembodiment. Accordingly, the invention has equal applicability to n-p-nphotodiodes comprising an p type charge collection region formedadjacent a p-type deep implanted region formed below a transistor array.Of course, the dopant and conductivity type of all structures willchange accordingly, with the transfer gate corresponding to a PMOStransistor. The invention has further applicability to p-n or n-pphotodiodes, that is, photodiodes that do not include a “pinned” or“surface” layer.

[0049] In addition, although the invention has been described above withreference to a transfer gate of a transfer transistor connection for usein a four-transistor (4T) pixel cell, the invention also hasapplicability to a three-transistor (3T) cell which differs from the 4Tcell in the omission of a charge transfer gate 130, the formation ofwhich was described above. In this case, the deep implanted region 199is still formed to be laterally adjacent a charge collection region 126.

[0050] The above description and drawings are only to be consideredillustrative of exemplary embodiments, which achieve the features andadvantages of the invention. Modification and substitutions to specificprocess conditions and structures can be made without departing from thespirit and scope of the invention. Accordingly, the invention is not tobe considered as being limited by the foregoing description anddrawings, but is only limited by the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. An image sensor comprising: a photosensorincluding a charge collection region of a first conductivity typelocated within a substrate; and an implanted region of a secondconductivity type, said implanted region being located laterally of saidphotosensor and adjacent-said charge collection region.
 2. The imagesensor of claim 1, wherein said photosensor is a photodiode.
 3. Theimage sensor of claim 2, wherein said photodiode is an n-p photodiode.4. The image sensor of claim 2, wherein said photodiode is a p-nphotodiode.
 5. The image sensor of claim 2, wherein said photodiode is ap-n-p photodiode.
 6. The image sensor of claim 2, wherein saidphotodiode is an n-p-n photodiode.
 7. The image sensor of claim 1,wherein said photosensor is a photogate.
 8. The image sensor of claim 1,wherein said photosensor is a photoconductor.
 9. The image sensor ofclaim 1, further comprising a gate structure of a transistor formed oversaid substrate, at least a portion of the bottom of said gate structurebeing in contact with said implanted region.
 10. The image sensor ofclaim 9, wherein said gate structure comprises a transfer transistorgate for transferring charge accumulated in said charge collectionregion to a floating diffusion region of said first conductivity type.11. The image sensor of claim 9, wherein said gate structure is a resetgate.
 12. The image sensor of claim 1, wherein said implanted region hasa thickness of about 0.5 microns to about 7.0 microns.
 13. The imagesensor of claim 12, wherein said implanted region has a thickness ofabout 1.0 microns to about 5.0 microns.
 14. The image sensor of claim 1,wherein said implanted region is doped with a p-type dopant at a dopantconcentration of from about 1×10¹⁶ to about 1×10¹⁷ atoms per cm³. 15.The image sensor of claim 14, wherein said implanted region is dopedwith a p-type dopant at a dopant concentration of about 5×10¹⁵ to about5×10¹⁶ atoms per cm³.
 16. The image sensor of claim 1, wherein saidfirst conductivity type is p-type and said second conductivity type isn-type.
 17. The image sensor of claim 1, wherein said first conductivitytype is n-type and said second conductivity type is p-type.
 18. Aphotosensor for use in an imaging device, said photosensor comprising: afirst doped layer of a first conductivity type formed in a substrate; acharge collection region formed in said first doped layer foraccumulating photo-generated charge, said charge collection region beingof a second conductivity type and being laterally adjacent an implantedregion of said first conductivity type; and a second doped layer of saidfirst conductivity type formed in said first doped layer and above saidcharge collection region.
 19. The photosensor of claim 18, wherein saidphotosensor is a photodiode.
 20. The photosensor of claim 19, whereinsaid photodiode is an n-p photodiode.
 21. The photosensor of claim 19,wherein said photodiode is a p-n photodiode.
 22. The photosensor ofclaim 19, wherein said photo diode is a p-n-p photodiode.
 23. Thephotosensor of claim 19, wherein said photodiode is an n-p-n photodiode.24. The photosensor of claim 18, wherein said photosensor is aphotogate.
 25. The photosensor of claim 18, wherein said photosensor isa photoconductor.
 26. The photosensor of claim 18, wherein saidimplanted region is in contact with said charge collection region. 27.The photosensor of claim 18 further comprising a gate of a transistorformed over said substrate, at least a portion of the bottom of saidgate being in contact with said implanted region.
 28. The photosensor ofclaim 27, wherein said gate is a reset gate.
 29. The photosensor ofclaim 18 further comprising a transfer gate of a transfer transistoradjacent said charge collection region, said transfer gate transferringcharge accumulated in said charge collection region to a doped region ofsaid second conductivity type.
 30. The photosensor of claim 18, whereinsaid implanted region is doped with a p-type dopant at a dopantconcentration of from about 1×10¹⁶ to about 1×10¹⁷ atoms per cm³. 31.The photosensor of claim 30, wherein said implanted region is doped witha p-type dopant at a dopant concentration of about 5×10¹⁵ to about5×10¹⁶ atoms per cm³.
 32. The photosensor of claim 18, wherein saidimplanted region has a thickness of about 0.5 microns to about 7.0microns.
 33. The photosensor of claim 32, wherein said implanted regionhas a thickness of about 1.0 microns to about 5.0 microns.
 34. Thephotosensor of claim 18, wherein said first conductivity type is p-typeand said second conductivity type is n-type.
 35. The photosensor ofclaim 18, wherein said first conductivity type is n-type and said secondconductivity type is p-type.
 36. An image sensor comprising: a siliconsubstrate; a shallow trench isolation region formed within said siliconsubstrate; a pixel within an area at least partially defined by saidshallow trench isolation region and comprising a photosensor, saidphotosensor further comprising a p-type pinned layer and an n-type dopedlayer located adjacent and below said p-type pinned layer; a channelregion of an adjacent transistor; and a p-type implanted region adjacentsaid n-type doped layer and said channel region.
 37. The image sensor ofclaim 36, wherein said photosensor is part of a 3T pixel cell.
 38. Theimage sensor of claim 36, wherein said photosensor is part of a 4T pixelcell.
 39. The image sensor of claim 36, wherein said transistor is atransfer transistor.
 40. The image sensor of claim 36, wherein saidtransistor is a reset transistor.
 41. The image sensor of claim 36,wherein said p-type implanted region is located along at least a portionof the bottom of said channel region.
 42. The image sensor of claim 36,wherein said n-type doped region is a floating diffusion region.
 43. Theimage sensor of claim 36, wherein said p-type implanted region has athickness of about 0.5 microns to about 7.0 microns.
 44. The imagesensor of claim 43, wherein said p-type implanted region has a thicknessof about 1.0 microns to about 5.0 microns.
 45. The image sensor of claim36, wherein said p-type implanted region has a dopant concentration offrom about 1×10¹⁶ to about 1×10¹⁷ atoms per cm³.
 46. The image sensor ofclaim 45, wherein said p-type implanted region has a dopantconcentration of about 5×10¹⁵ to about 5×10¹⁶ atoms per cm³.
 47. Animage sensor comprising: a silicon substrate; a shallow trench isolationregion formed within said silicon substrate; a pixel within an area atleast partially defined by said shallow trench isolation region andcomprising a photosensor; a channel region of an adjacent transistor;and an implanted region adjacent said photosensor and said channelregion.
 48. The image sensor of claim 47, wherein said photosensor is aphotodiode.
 49. The image sensor of claim 48, wherein said photodiode isa p-n-p photodiode, said p-n-p photodiode further comprising a p-typepinned layer and an n-type doped layer located adjacent and below saidp-type pinned layer.
 50. The image sensor of claim 47, wherein saidtransistor is a transfer transistor, said transfer transistortransferring charge accumulated in said n-type doped layer to anothern-type doped region.
 51. The image sensor of claim 50, wherein saidn-type doped region is a floating diffusion region.
 52. The image sensorof claim 47, wherein said implanted region is a p-type implanted regionlocated along at least a portion of the bottom of said channel region.53. The image sensor of claim 52, wherein said p-type implanted regionhas a thickness of about 0.5 microns to about 7.0 microns.
 54. The imagesensor of claim 53, wherein said p-type implanted region has a thicknessof about 1.0 microns to about 5.0 microns.
 55. The image sensor of claim47, wherein said implanted region has a dopant concentration of fromabout 1×10¹⁶ to about 1×10¹⁷ atoms per cm³.
 56. The image sensor ofclaim 55, wherein said implanted region has a dopant concentration ofabout 5×10¹⁵ to about 5×10¹⁶ atoms per cm³.
 57. An image sensorcomprising: a silicon substrate; a shallow trench isolation regionformed within said silicon substrate; a pixel within an area at leastpartially defined by said shallow trench isolation region and comprisinga p-n-p photodiode, said p-n-p photodiode further comprising a p-typepinned layer and an n-type doped layer located adjacent and below saidp-type pinned layer; a channel region of a transfer transistor, saidtransfer transistor transferring charge accumulated in said n-type dopedlayer to another n-type doped region; and a p-type implanted regionadjacent said n type doped layer and said channel region.
 58. The imagesensor of claim 57, wherein said p-type implanted region is locatedalong at least a portion of the bottom of said channel region.
 59. Theimage sensor of claim 57, wherein said n-type doped region is a floatingdiffusion region.
 60. The image sensor of claim 57, wherein said p-typeimplanted region has a thickness of about 0.5 microns to about 7.0microns.
 61. The image sensor of claim 60, wherein said p-type implantedregion has a thickness of about 1.0 microns to about 5.0 microns. 62.The image sensor of claim 57, wherein said p-type implanted region has adopant concentration of from about 1×10¹⁶ to about 1×10¹⁷ atoms per cm³.63. The image sensor of claim 62, wherein said p-type implanted regionhas a dopant concentration of about 5×10¹⁵ to about 5×10¹⁶ atoms percm³.
 64. An imager system comprising: a processor; and an imaging devicecoupled to said processor, said imaging device comprising: an isolationregion formed in a substrate; a pixel adjacent said isolation region,said pixel comprising a photosensor adjacent a gate structure of atransistor, said photosensor further comprising a layer of said firstconductivity type, and a doped region of a second conductivity typelocated below said layer; and an implanted region of said firstconductivity type laterally and adjacent said photosensor, and incontact with said doped region.
 65. The system of claim 64, wherein saidimplanted region has a thickness of about 0.5 microns to about 7.0microns.
 66. The system of claim 65, wherein said implanted region has athickness of about 1.0 microns to about 5.0 microns.
 67. The system ofclaim 64, wherein said first conductivity type is p-type and said secondconductivity type is n-type.
 68. The system of claim 64, wherein saidfirst conductivity type is n-type and said second conductivity type isp-type.
 69. The system of claim 64, wherein said photosensor is aphotodiode.
 70. The system of claim 69, wherein said photodiode is ann-p photodiode.
 71. The system of claim 69, wherein said photodiode is ap-n photodiode.
 72. The system of claim 69, wherein said photodiode isan n-p-n photodiode.
 73. The system of claim 69, wherein said photodiodeis a p-n-p photodiode.
 74. The system of claim 64, wherein saidphotosensor is a photogate.
 75. The system of claim 64, wherein saidphotosensor is a photoconductor.
 76. The system of claim 64, whereinsaid gate is a transfer gate for transferring charge accumulated in saiddoped region of said second conductivity type to a floating diffusionregion of said second conductivity type, said floating diffusion regionbeing opposite said doped region.
 77. The system of claim 64, whereinsaid gate is a reset gate.
 78. A method of forming a photosensor of apixel cell, said method comprising: forming a first doped layer of afirst conductivity type in said substrate; forming a doped region of asecond conductivity type in said first doped layer and between a gatestructure and an isolation region; and forming an implanted region ofsaid first conductivity type in said substrate, said implanted regionbeing lateral of and in contact with said doped region.
 79. The methodof claim 78, wherein said implanted region is formed along at least aportion of the bottom of said gate structure.
 80. The method of claim78, wherein said implanted region is formed by implanting a p-typedopant below at least a portion of said gate structure.
 81. The methodof claim 78, wherein said implanted region is doped with a p-type dopantat a dopant concentration of about 1×10¹⁶ to about 1×10¹⁷ atoms per cm³.82. The method of claim 81, wherein said implanted region is doped witha p-type dopant at a dopant concentration of about 5×10¹⁵ to about5×10¹⁶ atoms per cm³.
 83. The method of claim 78, wherein said implantedregion is formed to a thickness of about 0.5 microns to about 7.0microns.
 84. The method of claim 83, wherein said implanted region isformed to a thickness of about 1.0 microns to about 5.0 microns.
 85. Themethod of claim 78, wherein said act of forming said implanted regionfurther comprises forming a photoresist layer over said gate structureand said substrate, and patterning and etching said photoresist layer toexpose an area of said substrate located between said isolation regionand said doped region.
 86. The method of claim 85 further comprising theact of implanting a p-type dopant below said area of said substrate. 87.The method of claim 86 further comprising forming a second doped layerof said first conductivity type in said substrate and above said dopedregion.
 88. The method of claim 78, wherein said photosensor is aphotodiode.
 89. The method of claim 88, wherein said photodiode is ann-p photodiode.
 90. The method of claim 88, wherein said photodiode is ap-n photodiode.
 91. The method of claim 88, wherein said photodiode is ap-n-p photodiode.
 92. The method of claim 88, wherein said photodiode isan n-p-n photodiode.
 93. The method of claim 78, wherein saidphotosensor is a photogate.
 94. The method of claim 78, wherein saidphotosensor is a photoconductor.
 95. The method of claim 78, whereinsaid gate structure is a transfer gate.
 96. The method of claim 78,wherein said gate structure is a reset gate.
 97. A method of forming aphotosensor for an imaging device, said method comprising: forming agate of a transistor over a silicon substrate; forming a first p-typedoped layer in said silicon substrate; forming an n-type doped regionbelow said first p-type doped layer; and forming a doped region lateralof and in contact with said n-type doped region by implanting p-typeions below at least a portion of said gate and within an implant area ofsaid silicon substrate, said doped region having a dopant concentrationwithin the range of from about 1×10¹⁶ to about 1×10¹⁷ atoms per cm³. 98.The method of claim 97, wherein said doped region is formed along atleast a portion of the bottom of said gate.
 99. The method of claim 97,wherein said gate is a transfer gate of a transfer transistor.
 100. Themethod of claim 97, wherein said gate is a reset gate of a resettransistor.
 101. The method of claim 97, wherein said doped region isformed to a thickness of about 0.5 microns to about 7.0 microns. 102.The method of claim 101, wherein said doped region is formed to athickness of about 1.0 microns to about 5.0 microns.
 103. The method ofclaim 97, wherein said act of forming said doped region furthercomprises forming a photoresist layer over said gate and said substrate,and patterning and etching said photoresist layer to expose said implantarea of said substrate.
 104. The method of claim 103 further comprisingthe act of forming said implant area between said isolation region andsaid n-type doped region.
 105. The method of claim 104 furthercomprising the act of implanting a p-type dopant below said implant areaof said substrate.
 106. A method of forming a barrier implanted regionwithin a channel region of a transistor, said method comprising: forminga gate structure of a transistor over a substrate; forming source anddrain regions of a first conductivity type on opposite sides of saidgate structure, said source and drain regions forming a channel regionwithin said substrate and between said source and drain regions; andforming a barrier implanted region of a second conductivity type withinsaid channel region and adjacent said gate structure, said barrierimplanted region having a barrier dopant concentration higher than thesubstrate dopant concentration.
 107. The method of claim 106, whereinsaid barrier implanted region is formed by implanting ions below atleast a portion of said gate and within said substrate.
 108. The methodof claim 106, wherein said barrier implanted region has a dopantconcentration within the range of from about 1×10¹⁶ to about 1×10¹⁷atoms per cm³.
 109. The method of claim 108, wherein said barrierimplanted region has a dopant concentration of about 5×10¹⁵ to about5×10¹⁶ atoms per cm³.
 110. The method of claim 106, further comprisingthe step of forming a charge collection region of said firstconductivity type lateral of and adjacent said barrier implanted region.111. The method of claim 106, wherein said gate structure is a transfergate.
 112. The method of claim 106, wherein said gate structure is areset gate.